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Volume 1 | Issue 3 | Year 2011 | Article Id. IJCOT-V1I3P308 | DOI : https://doi.org/10.14445/22492593/IJCOT-V1I3P308
Digital and Mixed Signal Testing Technology The Standards IEEE 1149.1 and IEEE 1149.4
Partha Garai, Chaitali Biswas Dutta
Citation :
Partha Garai, Chaitali Biswas Dutta, "Digital and Mixed Signal Testing Technology The Standards IEEE 1149.1 and IEEE 1149.4," International Journal of Computer & Organization Trends (IJCOT), vol. 1, no. 3, pp. 40-44, 2011. Crossref, https://doi.org/10.14445/22492593/ IJCOT-V1I3P308
Abstract
Among all the On - Chip built - in self - test (BIST) technologies, JTAG is the most well - known and widely used . In th is paper, the mechanism of basic JTAG (IEEE 1149.1) has been discussed . The pitfalls of the method are also discussed, some of which are rectified in the future standard, IEEE 1149.4 for Mixed Signal testing, which is also described here . Many of the valua ble research papers on the se standards are analyzed .
Keywords
EEE 1149.1, IEEE 1149.4, JTAG, Boundary Scan, BSDL, Mixed Signal, SoC.
References
[1] Adam W. Ley, “The integration of boundary-scan test
methods to a mixed-signal environment”, Proceedings of
International Test Conference, pp. 159 - 162, 1999
[2] R. Schuttert, A. Kumar, “On-chip mixed-signal test structures
re-used for board test”, Proceedings of International Test
Conference, 2004, ITC 2004, pp. 375 - 383, 2004
[3] Srividya Sundar, Bruce C. Kim, Toby Byrd, and Felipe
Toledo, "Low cost automatic mixed-signal board test using
IEEE 1149.4", IEEE International Test Conference, ITC
2007, 21-26 Oct. 2007, pp. 1 - 9, 2007
[4] “IEEE computer society, IEEE standard for a mixed-signal
test bus” - IEEE Std. 1149.4 1999, IEEE, New York, 1999
[5] Uroˇs Kaˇc, Franc Novak, Srecko Macek, and Marina Santo
Zarnik, “Alternative test methods using IEEE 1149.4”,
Proceedings of Design, Automation and Test in Europe
Conference and Exhibition 2000. pp. 463-467, 2000
[6] G.O.D. Acevedo, J. Ramirez-Angulo, "VDDQ: a built-in selftest scheme for analog on-chip diagnosis, compliant with the
IEEE 1149.4 mixed-signal test bus standard", Fourth IEEE
International Caracas Conference on Devices, Circuits and
Systems, pp. I026-1- I026-4, 2002
[7] Heiko Ehrenberg, "Reconfigurable tester hardware extends
jtag/boundary scan applications while simplifying ate setup",
IEEE Autotestcon, 2007, pp. 712-717, 2007
[8] Lee Whetsel, “A high speed reduced pin count jtag
interface”, IEEE International Test Conference, ITC '06, pp.
1-10, 2006
[9] Takahashi et al., "A CMOS gate array with 600 mb/s
simultaneous bidirectional I/0 circuits", IEEE Journal of
Solid State Circuits, vol. 30, no. 12, 1995.
[10] Ishibashi et al., "Simultaneous Bidirectional Transceiver
Logic", IEEE Micro, vol. 19, no. 1, pp. 14 - 19, 1999
[11] Takahashi et al., "A 110 Gb/s simultaneous bidirectional
transceiver logic synchronized with a system clock", ISSCC
1999, IEEE Journal of Solid-State Circuits, vol. 34, no. 11,
pp. 1526 - 1533, 1999
[12] E. Yeung, M.A. Horowitz, "A 2.4 Gb/s simultaneous
bidirectional parallel link with per pin skew compensation",
IEEE Journal of Solid-State Circuits, vol. 35, no. 11, pp. 1619
- 1628, 2000.
[13] Xin-Xin Wang, Li-Ping Liang, and Xing-Jun Wang, “A new
solution to implement multi-full-scan-chain test with JTAG”,
8th International Conference on Solid-State and Integrated
Circuit Technology, ICSICT apos '06, pp. 2155 - 2157, 2006.
[14] Bambang Suparjo, Adam Ley, Adam Cron, and Heiko
Ehrenberg, "Analog boundary-scan description language
(ABSDL) for mixed-signal board test", IEEE International
Test Conference, ITC apos '06, pp. 1 - 9, 2006.
[15] Bapiraju Vinnakola, “Analog and mixed-signal test", Prentice
Hall PTR, 1998
[16] Sule Ozev and Alex Orailoglu, "System-level test synthesis
for mixed-signal designs" IEEE transactions on Circuits and
Systems, Analog and Digital Signal Processing, vol. 48, no.
6, 2001
[17] Mohammed Ali Abd El-Halim, "An analog mixed signal test
controller", The Midwest Symposium on Circuits and
Systems, MWSCAS-2002, vol 1, pp. I-384 – 7, 2002
[18] Juha Hakkinen, Pekka Syril, Juha-Veikko Voutilainen, and
Markku Moilanen, "A frequency mixing and sub-sampling
based RF-measurement apparatus for IEEE 1149.4",
International Test Conference on International Test
Conference, pp. 551 - 559, 2004
[19] L. Green, "The alias theorems: practical under-sampling for
expert engineers", EDN magazine, pp. 97-105, 2001
[20] R. Mason, S. Ma, "Analog DFT using an under-sampling
technique", IEEE Design and Test of Computers, pp. 84-88,
1999
[21] Stephen Sunter, Ken Filliter, Joe Woo, and Pat McHugh, "A
general purpose 1149.4 IC with HF analog test capabilities",
IEEE International Test Conference, pp. 38-45, 2001
[22] Pekka Syri, Juha Hakkinen, and Markku Moilanen, "IEEE
1149.4 compatible ABMs for basic RF measurements",
Conference on Design, Automation and Test in Europe, vol.
1, pp. 172 - 173, 2005
[23] C. Jeffrey, R. Cutajar, S. Prosser, M Lickess, A. Richardson
and S. Riches, "The integration of on-line monitoring and
reconfiguration functions using IEEE 1149.4 into a safety
critical automotive electronic control unit", Conference on
Design, Automation and Test in Europe, vol. 3, pp. 153 - 158,
2005
[24] Hari V. Venkatanarayanan, Michael L. Bushnell, “An area
efficient mixed-signal test architecture for systems-on-achip”, 19th International Conference on VLSI Design held
jointly with 5th International Conference on Embedded
Systems Design, pp. 161 - 168, 2006
[25] José M. Ferreira, António M. Cardoso, and Manuel G.
Gericota, "An integrated framework to support remote IEEE
1149.1 / 1149.4 design for test experiments", International
Journal of Online Engineering (iJOE), vol. 2, no. 3, 2006
[26] Uroˇs Kaˇc and Franc Novak, Florence Azaïs, Pascal Nouet,
and Michel Renovell, "Extending IEEE std. 1149.4 analog
boundary modules to enhance mixed-signal test", IEEE
Transactions on Design and Test of Computers, vol. 20, no.
2, pp. 32-39, 2003
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