International Journal of Computer
& Organization Trends

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Volume 3 | Issue 6 | Year 2013 | Article Id. IJCOT-V3I11P113 | DOI : https://doi.org/10.14445/22492593/IJCOT-V3I11P113

Power Efficient Weighted Modulo 2n+1 Adder

C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu

Citation :

C.Venkataiah , C.Vijaya Bharathi , M.Narasimhulu, "Power Efficient Weighted Modulo 2n+1 Adder," International Journal of Computer & Organization Trends (IJCOT), vol. 3, no. 6, pp. 25-30, 2013. Crossref, https://doi.org/10.14445/22492593/ IJCOT-V3I11P113

Abstract

The comparison of three different architectures for modulo 2n +1 adders are introduced in this paper. The first two architecture can be implemented different power consumptions, while maintain the same delay. The partitioned Sklansky structure compared to previous architecture can be implemented less power consumptions, while maintain the different delay and gate counts. The modulo adder 2n +1 adders can be easily derived by adding extra logic of modulo 2 n -1 adder. Power efficient modulo 2n +1 adders are appreciated in a variety of computer applications such as cryptography,RNS. The modulo 2n +1 adder is synthesized using Xilinx 9.1i tool and implemented FPGA spartan2 kit. Keywords Sklansky-style parallel prefix adder, kogge-stone parallel prefix adder, FPGA Spartan 2 kit ,VLSI.

Keywords

Sklansky-style parallel prefix adder, kogge-stone parallel prefix adder, FPGA Spartan 2 kit ,VLSI. 

References

[1]. Efficient Weighted Modulo +1 Adders by Partitioned Parallel-Prefix Computation and Enhanced Circular Carry Generation Tso-Bing Juang*, Member, IEEE, Pramod Kumar Meher**, Senior Member, IEEE, and Chin-Chieh Chiu*, 2011.
[2]. T. –B. Juang, C. –C. Chiu and M. –Y. Tsai, “Improved area-efficient weighted modulo +1 adders design with simple correction schemes,”IEEE Transactions on Circuits and Systems II, Exp. Briefs Vol. 57, No.3, pp. 198-202, March 2010.
[3]. H. T. Vergos and C. Efstathiou, “A unifying approach for weighted anddiminished-1 modulo +1 addition,” IEEE Transactions on Circuits and Systems II, Exp. Briefs, Vol. 55, No. 10 , pp. 1041-1045, Oct. 2008.
[4]. H. T. Vergos and D. Bakalis, „„on the use of diminished-1 adders for weighted modulo +1 arithmetic components,?? Proc. 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools, pp. 752-759, Sept. 2008.
[5]. Design and Characterization of Parallel Prefix Adders using FPGAs David H. K. Hoe, Chris Martinez and Sri Jyothsna Vundavalli Department of Electrical Engineering the University of Texas, Tyler @2011 IEEE.
[6]. Nannarell, M Re, and G. C. Cardarilli, ”Tradeoffs between residue number system and traditional FIR filters,” Proc. of the IEEE International Symposium on Circuits and Systems (ISCAS), pp. 305-308, May 2001.
[7]. K. Kaluri, W. F. Leong, K. –H. Tan, L. Johnson, and M. Soderstrand,“FPGA hardware implementation of an RNS FIR digital filter, “Conference Record of the Thirty-Fifth Asilomar Conference on Signals, Systems and Computers, pp. 1340-1344, Nov. 2001.
[8]. M.Parimaladevi R.Karthi “Analysis of Power Efficient Modulo 2n +1 Adder Architectures” International Journal of Computer Applications (0975 – 8887) Volume 70– No.4, May 2013.